The present invention relates to MIS semiconductor devices capable of accomplishing a further miniaturization and operating with high speed and low power consumption, and to methods for fabricating the same.
With increasing packing density of a semiconductor device, MIS transistors in the device are requested to become miniaturized. To accomplish this request, a MIS transistor having a heavily-doped channel structure in which the dopant concentration of a channel region is made high is required (For example, Japanese Unexamined Patent Publication No. 08-250729).
Hereinafter, a conventional method for fabricating a MIS transistor will be described with reference to the accompanying drawings.
FIGS. 13A to 13C, 14A and 14B are sectional views showing process steps of the conventional method for fabricating a MIS transistor step by step.
First, as shown in FIG. 13A, indium (In) ions acting as a p-type dopant are implanted into a semiconductor substrate 200 made of p-type silicon at an implantation energy of 100 keV and a dose of about 1×1014/cm2. Thereafter, the resulting substrate is subjected to thermal treatment to form a p-diffused channel layer 203 in a channel formation region of the semiconductor substrate 200.
As shown in FIG. 13B, a gate oxide film 201 having a thickness of about 1.5 nm is then formed on the semiconductor substrate 200. On the gate oxide film 201, a gate electrode 202 is formed which is made of polysilicon having a thickness of about 150 nm.
Next, as shown in FIG. 13C, using the gate electrode 202 as a mask, arsenic (As) ions acting as an n-type dopant are implanted into the semiconductor substrate 200 at an implantation energy of 2 keV and a dose of about 5×1014/cm2, thereby forming n-type implantation layers 206A. Then, using the gate electrode 202 as a mask, boron (B) ions acting as a p-type dopant are implanted into the semiconductor substrate 200 at an implantation energy of 5 keV and a dose of about 2×1013/cm2, thereby forming p-type implantation layers 207A.
As shown in FIG. 14A, an insulating film of silicon nitride or the like having a thickness of about 50 nm is deposited on the implanted semiconductor substrate 200. The deposited insulating film is anisotropically etched to form sidewalls 208 on the side surfaces of the gate electrode 202.
As shown in FIG. 14B, using the gate electrode 202 and sidewalls 208 as a mask, arsenic ions acting as an n-type dopant are implanted into the semiconductor substrate 200 at an implantation energy of 15 keV and a dose of about 3×1015/cm2. The resulting semiconductor substrate 200 is subjected to high-temperature and short-time thermal treatment to form n-diffused source and drain layers 205 in regions of the semiconductor substrate 200 located at either side of the sidewalls 208. During this treatment, in regions of the semiconductor substrate 200 interposed between each of the n-diffused source and drain layers 205 and the p-diffused channel layer 203, n-diffused extension layers 206 are formed by the diffusion of the n-type implantation layers 206A. In regions of the semiconductor substrate 200 located below the n-diffused extension layers 206, p-diffused pocket layers 207 are formed by the diffusion of the p-type implantation layers 207A.
As described above, in order to miniaturize the MIS transistor without producing any short channel effect, the conventional fabricating method of the MIS transistor employs, as a dopant for forming the p-diffused channel layer 203, heavy ions of indium (In) having a larger mass number than boron (B) and in addition the conventional method has a tendency to increase the dose of indium ions.
When indium ions of high dose are implanted into the semiconductor substrate 200, however, the implanted region of the semiconductor substrate 200 is amorphized. This causes, in the subsequent thermal treatment for activation, formation of EOR (End-of-Range) dislocation loop defect layers (referred simply to as dislocation loop defect layers) in the vicinity of the lower side of the interface between the amorphous layer and the crystal layer. Indium contained therein segregates largely to the dislocation loop defect layers, so that the activation concentration of the p-diffused channel layer 203 decreases. As a result, the conventional method cannot provide a transistor having a desired dopant profile.
Moreover, if the dislocation loop defect layers are formed in the p-diffused channel layer 203, leakage current disadvantageously flows along the dislocation loop defect layers.
FIG. 15 illustrates the dopant profile of the p-diffused channel layer 203 taken along the A—A line in FIG. 13A. FIG. 15 plots the depth measured from the substrate surface in ordinate and the logarithm of the dopant concentration of indium in abscissa. As seen from the indium ion profile of FIG. 15, indium ions contained in the p-diffused channel layer 203 segregate by the thermal treatment to the dislocation loop defect layers formed in the vicinity of the amorphous-crystal interface.
As is apparent from the above, it is difficult for the conventional method for fabricating a semiconductor device to form a heavily-diffused channel layer, which is dispensable for a miniaturized transistor, to have a desired dopant concentration.